1. Field of the Invention
This invention relates to the production of patterns on a substrate having regions with different chemical identities. More particularly, it relates to a method of producing fine patterns on substrates used in, for example, the microelectronics industry on which electronic devices are fabricated. The present invention also relates to devices fabricated in accordance with these methods.
2. Description of the Related Art
A number of applications and technologies involve structures having a well-defined arrangement of distinct regions. Normally, these structures are defined by patterning processes such as lithography, embossing, and stamping, and have length scales ranging from nanometers to several microns to even millimeters. In many of these systems it may be necessary or beneficial to apply an additional component or treatment to or above only a subset of the chemically district regions. One commonly used technique for doing this is through the use of a mask to protect regions wherein this additional application or treatment is not desired. Effectively, the mask material directs this treatment to the intended surfaces that are fully exposed. Unfortunately, typical procedures used to generate a mask by lithographic or other means can be expensive and error prone particularly when alignment or overlay is required. Thus, techniques for circumventing these conventional approaches would be highly advantageous.
A particular example in which such strategies would be useful involves integrated circuits comprised of metal and dielectric components. It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area is increased. Throughout the semiconductor industry, there has been a strong drive to reduce the dielectric constant, k, of the dielectric materials existing between metal lines and/or to minimize the thickness of layers have comparatively larger dielectric constants, e.g., cap barrier layer.
Both of these approaches reduce the effective dielectric constant, keff, of the components between metal lines and as a result, interconnect signals travel faster through conductors due to a reduction in resistance-capacitance (RC) delays. Unfortunately, these strategies are difficult to implement due to limitations in maintaining sufficient properties, i.e., mechanical, barrier, electrical, etc., that result when there is a reduction in thickness or changes in the chemistry of the layers.